Implementation and Comparative Analysis of Various Low Power FSM Synthesis Techniques
Keywords:
FSM, Clock gating, FSM partitioning, Power consumption, Sequence Detector, Traffic Light ControllerAbstract
This paper discusses the implementation and comparative analysis of the techniques to lower the power consumption in Finite State Machines (FSMs). FSM partitioning and clock gating have been discussed and incorporated in two modules: sequence detector and traffic light controller to investigate their performance in terms of power consumption and thus identify the most effective approach. The FSM Partitioning technique works in conjunction with the heuristic algorithm approach to decompose a single FSM into two separate FSMs. Thus, power consumption can be reduced since only one sub-machine is clocked at any given time while the other remains inactive, resulting in decreased power dissipation for the overall circuit. Additionally, the Clock Gating technique is introduced, which involves disabling the clock signal to the sequential blocks of the FSM during periods of inactivity or idleness. These techniques have been implemented and simulated in the aforementioned circuits using the XILINX_ISE_14.7. It has been found that FSM Partitioning results in a power saving of 72% and 87.5% when applied to a 5-bit sequence detector and a traffic light controller, respectively, compared to the conventional design. Similarly, applying clock gating techniques results in power savings of 33% and 75% for a 5-bit sequence detector and a traffic light controller, respectively, compared to the conventional design. This work presents two techniques that yield a good amount of power saving in both case studies of sequence detector and traffic light controller. Also, the better effectiveness of FSM partitioning technique has been established.
References
[1] V. Taraate, “FSM designs”, In Digital Design from the VLSI Perspective: Concepts for VLSI Beginners. p. 177-191. Springer Nature. Singapore. 2022. https://doi.org/10.1007/978-981-19-4652-3_12
[2] M. T. Morazán, “Deterministic Finite-State Machines”, In Programming-Based Formal Languages and Automata Theory: Design, Implement, Validate, and Prove. p. 87-131. Cham: Springer Nature. Switzerland. 2023. https://doi.org/10.1007/978-3-031-43973-5_5
[3] M. T. Morazán, “Nondeterministic Finite-State Machines”, In Programming-Based Formal Languages and Automata Theory: Design, Implement, Validate, and Prove. p. 133-165. Cham: Springer Nature. Switzerland. 2023. https://doi.org/10.1007/978-3-031-43973-5_6
[4] V. Taraate, “FSM Design Techniques”, In Digital Design Techniques and Exercises: A Practice Book for Digital Logic Design. p. 137-151. Springer. Singapore. 2021. https://doi.org/10.1007/978-981-16-5955-3_9
[5] Q. Ningning and X. Baoguo, “Research on FSM for the wireless communication”, In 2010 2nd International Conference on Future Computer and Communication. 2010; 2: p. V2-417. IEEE. doi: 10.1109/ICFCC.2010.5497464.
[6] M. Ben-Ari and F. Mondada, “Finite state machines”, In Elements of Robotics, p. 55-61. Springer, Cham. 2018. https://doi.org/10.1007/978-3-319-62533-1_4
[7] A. Barkalov, L. Titarenko, J. Bieganowski and K. Krzywicki, “Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review”, Applied Sciences. 2024; 14(7): p. 2693. https://doi.org/10.3390/app14072693
[8] P. Bhattacharjee and A. Majumder, “LECTOR based gated clock approach to design low power FSM for serial adder”, In 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS). 2016; p. 250-254. IEEE. doi: 10.1109/iNIS.2016.064.
[9] G. Ashutosh, M. Jivan, G. Shraddha and P. Rahul, “Reducing Clock Power by Using the Clock Gating Technique”, In Techno-Societal 2016, International Conference on Advanced Technologies for Societal Applications. 2016; p. 919-926. Cham: Springer International Publishing. https://doi.org/10.1007/978-3-031-34644-6_94.
[10] A. Saleem and S. A. Khan. “Low power state machine design on FPGAs”, In 2010 3rd international conference on advanced computer theory and engineering (ICACTE). 2010; 4: p. V4-442. IEEE. doi: 10.1109/ICACTE.2010.5579416.
[11] A. Nag, S. Das and S. N. Pradhan, “Low-power FSM synthesis based on automated power and clock gating technique”, Journal of Circuits, Systems and Computers. 2019; 28(05): p. 1920003. https://doi.org/10.1142/S0218126619200032
[12] D. Mihhailov, A. Sudnitson and K. Tarletski, “Web-based tool for FSM encoding targeting low-power FPGA implementation”, In 2010 27th International Conference on Microelectronics Proceedings. 2010; p. 349-352. IEEE. doi: 10.1109/MIEL.2010.5490468.
[13] S. Li and K. Choi, “A high performance low power implementation scheme for FSM”, In 2014 International SoC Design Conference (ISOCC). 2014; p. 190-191. IEEE. doi: 10.1109/ISOCC.2014.7087690.
[14] A. Klimowicz and T. Grzes, “Combined State Merging and Splitting Procedure for Low Power Implementations of Finite State Machines”, In Advances in Systems Engineering: Proceedings of the 28th International Conference on Systems Engineering, ICSEng 2021, December 14-16, Wrocław, Poland. 2022; p. 190-199. Springer International Publishing. https://doi.org/10.1007/978-3-030-92604-5_17
[15] P. Choudhury and S. N. Pradhan, “Power modeling of power gated FSM and its low power realization by simultaneous partitioning and state encoding using genetic algorithm”, In Progress in VLSI Design and Test: 16th International Symposium, VDAT 2012, July 1-4, Shibpur, India. 2012. p. 19-29. Springer Berlin Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_3.
[16] A. Bukowiec and L. Gomes, “Partitioning of Mealy finite state machines”, IFAC Proceedings Volumes. 2009; 42(21): p. 19-24. https://doi.org/10.3182/20091006-3-ES-4010.00006
[17] J. E. Ortiz and R. H. Klenke, “Simple traffic light controller: A digital systems design project”, In Proceedings of the IEEE SoutheastCon. 2010; p. 85-88. IEEE. doi: 10.1109/SECON.2010.5453915.
[18] B. J. LaMeres, “Modeling Finite-State Machines. In Quick Start Guide to VHDL”, 2023; p. 127-141. Cham: Springer International Publishing. https://doi.org/10.1007/978-3-031-44104-2_8.
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