A 32-Bit Ripple-Ling Hybrid Carry Adder
DOI:
https://doi.org/10.69996/fmep.2026001Keywords:
32-bit Ripple-Ling Hybrid Carry Adder, Arithmetic Logic Unit (ALU), Ripple Carry Adder (RCA), Ling-based parallel prefix tree, Look-Up Table (LUT) utilizationAbstract
This paper explores the design and implementation of a 32-bit Ripple-Ling Hybrid Carry Adder, aimed at optimizing the balance between hardware resource utilization and computational throughput. In wide-word arithmetic units, the carry propagation delay of high-order bits typically dominates the critical path. The proposed architecture addresses this by employing a non-uniform partitioning strategy: the low-order 11 bits are implemented using a Ripple Carry Adder (RCA) structure to minimize area and static power consumption, while the high-order 21 bits utilize a Ling-based parallel prefix tree. . The architecture was modeled in VHDL and evaluated using the Xilinx Vivado synthesis tool. Experimental data reveals a significant reduction in Look-Up Table (LUT) utilization compared to conventional ripple-carry architectures, demonstrating the effectiveness of the hybrid approach for resource-constrained digital systems. The results provide a comparative analysis of power consumption and area efficiency, establishing the Ripple-Ling hybrid adder as a viable candidate for energy-efficient arithmetic logic unit (ALU) design.
References
[1] N. Shang, "A 32-Bit Ripple-Ling Hybrid Carry Adder," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 6, pp. 2485-2496, 2024.
[2] H. Ling, "High-Speed Binary Adder," IBM Journal of Research and Development, vol. 25, no. 3, pp. 156-166, 1981.
[3] R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders," IEEE Transactions on Computers, vol. C-31, no. 3, pp. 260-264, 1982.
[4] S. Winograd, "On the Time Required to Perform Addition," Journal of the ACM (JACM), vol. 12, no. 2, pp. 277-285, 1965.
[5] N. T. Quach and M. J. Flynn, "High-Speed Addition in CMOS," IEEE Transactions on Computers, vol. 41, no. 1, pp. 122-126, 1992.
[6] PoojaPuri, “Knowledge and Innovation Management in Higher Education”, JCESH, vol. 2, no. 3, pp. 63–71, 2025
[7] Vivado Design Suite User Guide: Synthesis, UG901 (v2023.2), Xilinx Inc., Oct. 2023.
[8] Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics, DS181, Xilinx Inc., 2020.
[9] S. Knowles, "A Family of Adders," Proceedings 15th IEEE Symposium on Computer Arithmetic, pp. 277-281, 2001.
[10] N. Burgess, "A Long-Operand Hybrid Carry-Lookahead/Carry-Select Adder," IEEE Transactions on Computers, vol. 60, no. 9, pp. 1211-1221, 2011.
[11] J. Grad and J. E. Stine, "A High-Speed Low-Power 32-Bit Carry Look-Ahead Adder," IEEE International Conference on Circuit Theory and Design, vol. 2, pp. 241-244, 2004.
[12] M. Ziegler and M. Stan, "Optimal Hybrid Design of Low Power and High Performance Adders," Proceedings of the 14th ACM Great Lakes Symposium on VLSI, pp. 259-264, 2004.
[13] K. Vitushinsky and S. Oberman, "High-Speed Floating-Point Adder Design," Proceedings 15th IEEE Symposium on Computer Arithmetic, pp. 13-20, 2001.
[14] T. Han and D. A. Carlson, "Fast Area-Efficient VLSI Adders," 8th IEEE Symposium on Computer Arithmetic (ARITH), pp. 49-56, 1987.
[15] V. G. Oklobdzija, "High-Speed VLSI Arithmetic Units: Adders and Multipliers," in The VLSI Handbook, 2nd ed., CRC Press, 2006.
[16] 7 Series FPGAs Configurable Logic Block User Guide, UG474, Xilinx Inc., vo1.8, 2016.
