Implementation and Comparative Analysis of Various Low Power FSM Synthesis Techniques (Journal of Electronics and Power Engineering (JEPE), 2025)
This paper discusses the implementation and comparative analysis of the techniques to lower the power consumption in Finite State Machines (FSMs). FSM partitioning and clock gating have been discussed and incorporated in two modules: sequence detector and  traffic light controller to investigate their performance in terms of power consumption and thus identify the most effective approach. The FSM Partitioning technique works in conjunction with the heuristic algorithm approach to decompose a single FSM into two separate FSMs. Thus, power consumption can be reduced since only one sub-machine is clocked at any given time while the other remains inactive, resulting in decreased power dissipation for the overall circuit. Additionally, the Clock Gating technique is introduced, which involves disabling the clock signal to the sequential blocks of the FSM during periods of inactivity or idleness. These techniques have been implemented and simulated in the aforementioned circuits using the XILINX_ISE_14.7. It has been found that FSM Partitioning results in a power saving of 72% and 87.5% when applied to a 5-bit sequence detector and a traffic light controller, respectively, compared to the conventional design. Similarly, applying clock gating techniques results in power savings of 33% and 75% for a 5-bit sequence detector and a traffic light controller, respectively, compared to the conventional design. This work presents two techniques that yield a good amount of power saving in both case studies of sequence detector and traffic light controller. Also, the better effectiveness of FSM partitioning technique has been established.